1. Field of the Invention
The present invention relates to a digital signal processing apparatus and method thereof, which reproduce impulse responses on the basis of the characteristic of the signal transfer between two broadcasting systems. The invention also relates to a headphone apparatus in which the apparatus and method are used.
2. Description of the Related Art
When an audio signal is supplied to a speaker and the speaker playback the music, the resultant acoustic image lies in front of the listener. When the same audio signal is supplied to the headphone that the listener wears, the acoustic image lies in the listener's head. This is extremely unnatural positioning of the acoustic image.
A headphone apparatus that positions the acoustic image outside the listener's head has been proposed, as is disclosed in Japanese Patent Application Laid-Open Publication No. 11-331992 corresponding to a Japanese patent application filed by the assignee of the present application. FIG. 1 illustrates such a headphone apparatus. As shown in FIG. 1, an analog audio signal SA is supplied via the input terminal 1 to an A/D converter circuit 2, which converts the audio signal to a digital audio signal SD. The signal SD is supplied to digital signal processing circuits 3L and 3R. These processing circuit 3L and 3R process the signal SD so that the resultant acoustic image may lie outside the listener's head.
If a sound source SP is located in front of a listener M as shown in FIG. 2, the sound output from the source SP is transferred to the listener's left and right ears though a path that has transfer functions HL and HR.
In the digital signal processing circuits 3L and 3R, the impulse responses obtained by converting the transfer functions HL and HR to time axes are convoluted in the signal SD. The impulse responses can be either measured or calculated.
Performing this convolution, the digital signal processing circuit 3L generates a signal, and so does the digital signal processing circuit 3R. The signal generated by the circuit 3L is supplied to a D/A converter 4L, which converts the signal to an analog audio signal SA. Similarly, the signal generated by the circuit 3R is supplied to a D/A converter 4R, which converts the signal to an analog audio signal SA. The analog audio signals SA are supplied via headphone amplifiers 5L and 5R to the left and right acoustic units (electro-acoustic transducer) 6L and 6R of a headphone 6, respectively.
The sound reproduced by the headphone 6 is therefore one coming through the path that has transfer functions HL and HR. When the listener M wearing the headphone 6 listens to the sound, he or she feels that the acoustic image SP lies outside his or her head as is illustrated in FIG. 2.
To provide the transfer functions HL and HR, the digital signal processing circuits 3L and 3R have such a FIR filter configuration as shown in FIG. 3. In this configuration, the digital audio signal SD generated by the A/D converter circuit 2 (FIG. 1) is supplied via the input terminal 31 to a plurality of delay circuits 3D that are connected in series. The signal output from the input terminal 31 is supplied to a multiplier circuit 3M. The signals output from the delay circuits 3D are supplied to other multiplier circuits 3M, respectively. The outputs of the multipliers 3M are output to the output terminal 37 via adder circuits 3A, respectively.
Each delay circuit 3D delays the digital audio signal SD by one-sampling period (unit period) τ. Each multiplier circuit 3M has, as a coefficient, the impulse response at any time when the transfer function HL or HR is converted to a time axis.
It is therefore necessary to use many taps (i.e., orders) in the digital signal processing circuits 3L and 3R, both shown in FIG. 3. That is, the circuits 3L and 3R must have many delay circuits 3D and many multiplier circuits 3M. For example, 1024 delay circuits and 1024 multiplier circuits must be incorporated in either digital signal processing circuit.
If the digital signal processing circuits 3L and 3R are constituted by a DSP each, they will need a large-capacity memory for the delay circuits 3D. Inevitably, the IC scale of circuits 3L and 3R becomes large, proportionally increasing the manufacturing cost of the circuits 3L and 3R. Further, the process steps increase because the circuits 3L and 3R require a great number of multiplier circuits 3M each. Consequently, signals must be processed at high speed in the circuit 3L and 3R. This raises the operating cost of the digital signal processing circuits 3L and 3R.